Exemplary embodiments of the present invention relate to a semiconductor memory device.
As the development of the technology for computer systems or electronic communications has steadily evolved, semiconductor memory devices used for storing information have become cheaper, physically smaller, and larger with respect to data capacity. As a result, increasing demands for efficient energy consumption are being imposed on these types of semiconductor memory devices in order to cut down unnecessary current dissipation.
A general cell array layout for storing data in dynamic random access memory (DRAM) semiconductor devices is usually configured to include a plurality of memory cells coupled to word and bit lines which usually form a web- or matrix-like structure. Each memory cell is usually composed of one transistor and one capacitor.
In a row decoding operation, a row address strobe (/RAS) signal, which is one of main signals for operating a DRAM semiconductor device, changes to an active state (low level), and a row address buffer receives row address signals. One word line of a cell array is then selected by decoding the received row address signals.
Data which are stored in memory cells coupled to the selected word line are loaded into a bit line pair (BL, /BL). A sense amplifier enable signal which informs a sense amplifier operation start time is enabled to operate a sense amplifier driving circuit of a cell block which is selected by the row addresses. The sense amplifier driving circuit changes a sense amplifier bias voltage to a core voltage (VCORE) and a ground voltage (VSS), and drives a sense amplifier latch. When the sense amplifier latch begins to operate, the bit line pair (BL, /BL) having maintained a slight potential difference changes to a large potential difference. A column decoder which is then selected by column addresses turns on column transfer transistors to transfer data of the bit line pair (BL, /BL) through data bus lines to the outside of the semiconductor memory device.
In these operations, the bit line pair (BL, /BL) is precharged to a bit line precharge voltage (VBLP) while in a standby mode before the semiconductor memory device begins to operate. When the semiconductor memory device begins to operate, the data of the memory cells are transferred and then change to different potentials having a slight potential difference. In such a state, when the sense amplifier latch begins to operate, the potentials of the bit line pair (BL, /BL) having maintained a slight potential difference change to a core voltage (VCORE) and a ground voltage (VSS), respectively. In this manner, the amplified data of the bit lines (BL, /BL) are transferred to data bus lines (DB, /DB) in response to a column decoder output signal (Yi). However, when the sense amplifier latch receives the core voltage (VCORE) as a sense amplifier bias voltage and begins to operate, a large amount of current is abruptly consumed. Consequently, the core voltage (VCORE) rapidly drops. In this case, when the sense amplifier latch begins to operate, an external voltage (VDD) is supplied as the core voltage (VCORE) by shorting the external voltage (VDD) and the core voltage (VCORE). This operation is called a sense amplifier overdriving.
Meanwhile, as illustrated in FIG. 1, a plurality of memory cell arrays and a plurality of sense amplifier arrays are disposed in the semiconductor memory device. Also, a plurality of sub word line drivers (SWD) are provided to selectively drive the memory cell arrays. In the semiconductor memory device layout illustrated in FIG. 1, regions between the sense amplifier arrays are called sub hole regions (SH), and both end regions are called edge regions.